Reference is made to the article “A 4.8-6.4 Gbps Serial Link for Back-plane Applications using Decision Feedback Equalization” by the same inventors identified herein, published at Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, pages 31-34, October 2004, the content of which is hereby incorporated by reference in its entirety.
Copper traces on printed circuit boards (PCBs) are used as data channels to transmit digital data from a transmitting unit to a receiving unit on the PCB. These traces exhibit several loss mechanisms that degrade the data signal and generate inter-symbol interference (ISI) between data bits in a data string or bit stream. These loss mechanisms include skin effect, dielectric loss, and reflections from impedance discontinuities in the traces. These losses increase as data communication speeds increase. ISI increases with increased data speeds, resulting in increased bit error rates (BERs) and degradation of clock signals recovered from received data.
Advanced equalization techniques are employed to reduce ISI and recover data and clock from the data stream at the receiver. Some designs implement pre-emphasis to increase high-frequency gain of the transmitted signal to compensate for increased high-frequency losses though the channel. Other designs employ linear equalizers, such as finite impulse response (FIR) filters, to boost the high-frequency signals in the receiver. Yet other designs employ both transmitter pre-emphasis and receiver equalization. However, these techniques also boost high frequency noise and cross-talk, which can degrade performance. Moreover, cross-talk, which is already greater at higher frequencies, gets worse due to high frequency boost from the transmitter pre-emphasis and by the equalizer at the receiver.
An improved equalization technique is illustrated in FIG. 1, and employs a decision feedback equalizer (DFE) at the receiver that removes post-cursor ISI due to channel losses by feeding back decisions that are clean. As shown in FIG. 1, data transmitted by transmitter 10 are received from data channel 12 by receiver 14. Data, which may be distorted due to loss mechanisms in channel 12, are received by a forward equalizer 16. Forward equalizer 16 conditions the received signal by adjusting the signal gain so that the signal amplitude of data signals forwarded to summing device 18 is substantially constant. Data slicer 20 provides decisions to DFE 22 to supply a signal to summing device to cancel inter-symbol interference caused by the most recently processed bits from the presently received bit. An adaptive loop drives forward equalizer 16 and DFE 22 for optimal settings for given channel loss characteristics.
Data slicer 20 is timed by the clock recovered from the output data to provide clean decisions ±1 in the case of binary non-return to zero (NRZ) signaling. The decisions are fed back to DFE 22 to minimize ISI in subsequent bits. More particularly, the output from slicer 20 is applied to a voltage-controlled oscillator loop (not shown) to recover the clock signal in a well-known manner. The filter coefficients of forward equalizer 16 and DFE 22 are driven by the adaptation loop and set according to the most optimal settings for given channel loss characteristics that result in the lowest BER. In PCB applications, a target BER of 10−15 is typical.
The DFE system shown in FIG. 1 minimizes BER loss without boosting noise or cross-talk to achieve signal equalization. However, the system uses previous decisions to cancel ISI in the present bit. Consequently, the system is vulnerable to error-propagation.
The DFE system shown in FIG. 1 must be linear over the entire operating range of the circuit. Forward equalizer 16 requires considerable power to operate in a linear mode over a wide high frequency range. Thus, power limitations at the receiver end of channel 12 effectively eliminate implementation of the DFE system of FIG. 1 in PCBs and integrated circuit (IC) chips for wide high frequency ranges, such as at frequencies of 4.8 to 6.4 gigabits per second (Gbps). There is a need, therefore, for a data transmission system that is linear over a high frequency range and that does not require considerable power at the receiver.